An integrated circuit (IC) has a large number of electronic components, such as transistors, logic gates, diodes, and wires that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer.
Many phases of physical design may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language.
An EDA system typically receives the high level behavior descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction using a computer synthesis process. A netlist describes interconnections of nodes and components on the chip and includes information of circuit primitives, such as for example, transistors and diodes, their sizes and interconnections.
An integrated circuit designer may use a set of layout EDA application programs to create a physical design of the IC from the logical design. The layout EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes. The geometric information about the placement of the nodes and components onto the chip may be determined by a placement process and a routing process. The placement process is a process for placing electronic components or circuit blocks on the chip and the routing process is the process for creating interconnections between the blocks and components according to the specified netlist.
The problem being addressed by the present invention is caused by the tendency of many modem electronic designs to become extremely large, with larger die sizes and more complex floorplans. This results in longer connections between routing end-points within the electronic designs, so that it is becoming impossible for an unassisted signal to travel from one end-point to another in a single clock cycle.
To address this problem, the electronic designer inserts pipeline flip-flops or pipeline registers (hereinafter collectively referred to as “pipeline flip-flops”) between start-points and end-points in a route between two points. In this way, the signals transmitted between the two points will be kept in proper synchronization for the given clock cycles.
FIG. 1 shows a very simple example of this process, in which a designer is required to route a net between Macro A and Macro B. The “before” situation is shown at the top part of the figure, in which it can be seen that there is a 10 mm distance between Macro A and Macro B. Assume that this distance is too long to allow a signal to get from Macro A to Macro B within a single clock cycle. To address this problem, the designer could create a revised routing scheme by inserting three pipeline flip-flops 10a, 10b, and 10c along the route, with equal distances of 2.5 mm between any two points along the revised route, which is shown in the “after” situation at the bottom of the figure.
Conventionally, the process to insert pipeline flip-flops into a design is highly manual in nature, with a designer commonly required to individually consider and analyze nets in the design to determine where and when pipeline flip-flops need to be inserted into the design. This is a tedious and error-prone task if performed manually. Moreover, if there are a very large number of nets in a design (which is likely given that the present problem arises because of larger and more complex designs), then the amount of effort needed to perform the analysis may become overwhelming. The task for the design is further complicated by the fact that many nets in the design are not routed along nicely straight routing paths as shown in FIG. 1. Instead, as shown in FIG. 2, many routing paths extend along complex and winding paths, making it even more difficult for a designer to determine the ideal pipeline flip-flop positions for the routing path.
Therefore, as is evident from the above discussion, there is a need for an improved approach for placement of pipeline flip-flops in an electronic design.